The MegaCART is a cart design based around a 27C080 EPROM. One full Mbyte can be used for data storage accessible from every code position. 768 KByte can be used for code execution. The bank switching methods used are based on a combination of the bank switching in some of the commercial carts (Videopac 31, 40, 55, 58, 59, 60) for data and code, but are not fully compatible. The MegaCART PCB fits into a standard Videopac cart case.
The MegaCART is also the base for a flash ROM based cart design called FlashCART.
The MegaCART is completely incompatible with The Voice
. The bank
switch registers collide, I use address line 10 and the T0 on the
FlashCART. The only way around this is to design a new, different voice
cart.
This is a picture of a MegaCART. Click on it for a bigger picture. This is
version 1.4, the version you can download below. I have soldered it with
lead-free solder. The EEPROM is a 93C46. The cart is configured for a
27C080 EPROM.
The MegaCART supports all EPROM sizes between 27C64 and 27C080. The default configuration is for 27C080, the smaller sizes can be selected by solder jumpers.
There is room for a 93CX6 EEPROM to store highscores and settings. The MegaCART supports EEPROMs with 5V Vcc and 8 bit wide storage. The 3V versions from most manufacturers can be run with 5V, too. EEPROMs which can be switched between 8 bits and 16 bits by pin 6 are set to 8 bits. A hardware write protection by pin 7 is bypassed. These EEPROMs are bit serial, the pins go to I/O ports on the MegaCART. The software inside the MegaCART has to do all the clock, data and chip select by itself. Some example code is included into the package.
All the bank switch logic is inside one Xilinx XC9572XL CPLD. This is a 3V chip, so there is a 3V regulator, too. The CPLD needs to be programmed through its JTAG port. This can be done using either the Xilinx iMPACT software or any JTAG control software which understands SVF or XSVF files.
The MegaCART has 4 hardware registers accessible as external RAM
starting at 080h. Although they are mirrored every 4 bytes I suggest to
only use the copies from 080h-083h, future hardware may have more
registers. The code bank switch method for code is based on the one used for
12K and 16K Videopac+ games. The data bank switch is similar to the one
used on Videopac 31 and 40, Musician
and 4 in 1 Row
.
All three read/write registers return the last value written to them when read.
ereg_codebankThis read/write register stores the current code bank. This sets the
address line A12-A19 for program code if P1.0 is 0. If P1.0 is set address
lines A12-A19 are all ones, so after reset bank 0ffh is active. The
ereg_codebank contains 0 after the BIOS routine
init is run. So it makes sense to first write 0ffh into
ereg_codebank and then clear P1.0 as part of an early
initialisation. In all banks the BIOS is still at 0-03ffh.
The way the code bank switch works is not compatible with the automatic
Videopac+ detection used by plusselectgame. If you use the
firmware you can check the iram_mode_plus bit, or check the BIOS
by a direct read like in the following example:
; detect videopac+
; The bank-switch of the MegaCART is not compatible with the usual
; way to detect VP+, so I check one of the two easily readable
; differences in the BIOS. (The other one is 0394h=0bbh for VP+)
section plusdetect
mov a,#07eh
movp3 a,@a ; read 037eh, 020h=std, 039h=VP+
xrl a,#039h
jz .ok
jmp normal ; no videopac+
.ok endsection plusdetect
ereg_databankThis read/write register stores the current data bank. This sets the
address line A12-A19 for data reads if P1.1 is 0. Additionally A8-A11 have
to be set by the lowest nibble of P2. Then the XROM read of the EPROM is
activated by a movx read. All the other read sources have to
be turned off: VDC, VPP and external RAM. Since the BIOS knows P1.1 only as
address line for its own bank switching, P1.1 has to be set manually before
using any other of the movx sources, the BIOS routines don't
do it.
This XROM read allows reading all bytes of the EPROM from any code location. It simplifies the handling of big data structures like Videopac+ data. The BIOS interrupt routines do not know about the XROM access, so you have to disable the interrupts while P1.1 is cleared.
Here are some macros I wrote to enable and disable XROM data read. More code can be found in my G7000 BIOS document. A full example program is on the demo program page.
; Enable XROM (read and write)
; P16=0 (enable cart signal), P11=0 (enable XROM), P15=1, P14=1, P13=1, P12=1
m_xromenable macro
orl P1,#03ch
anl P1,#0bdh
endm
; Disable XROM reading: P11=1
; This is needed because the BIOS extram/vdcenable routines don't touch P10/P11
m_xromdisable macro
orl P1,#002h
endm
; Switch from XROM to XRAM
m_xromtoram macro
orl P1,#0beh
anl P1,#0afh
endm
ereg_io_outThis read/write register is used to control some pins on the CPLD. Three of them are connected to the EEPROM, one is used on the FlashCART for communication. I strongly suggest that you insert the FlashCART firmware into your program if your want to use the EEPROM or talk to a PC.
| Bit 0 | eout_tx | This bit is used on the FlashCART as TX line. It is inverted, so that the BIOS initialises it to the correct level on the serial port. |
|---|---|---|
| Bit 1 | eout_eecs | This bit controls the chip select pin of the EEPROM. |
| Bit 2 | eout_eeclk | This bit controls the clock pin of the EEPROM. |
| Bit 3 | eout_eedi | This bit controls the data in pin of the EEPROM. |
All the eout_ definitions are bit masks,
not bit numbers.
ereg_io_inThis is a read only register which contains the level on some of the CPLD pins. Currently only one bit is used, the rest returns 0.
| Bit 0 | ein_eedo | This bit reads the data out pin of the EEPROM. |
|---|
As usual I release everything you need to build your own MegaCART. I currently do not intend to produce them myself, but I am willing to give you some help, just send an E-Mail.
You need to be able to make your own PCBs or have some professional PCB company make them for you. All parts except the EEPROM are SMD, so it is even possible to machine-place the whole MegaCART. All parts are available in RoHS-compliant versions.
If you solder the parts by hand you need some soldering skills. The CPLD has a pin spacing of 0.8mm. The resistors and decouple caps are 0603, 1.6mm × 0.8mm. The JTAG connector is tricky, too. Its leads have a strange form, they are much higher than wide.
You also need a JTAG programmer. Xilinx has released the schematic to their
Programming Cable III. It is good enough for the XC9572XL chip in the
MegaCART. Then you can use the iMPACT software you can download on their
homepage to program the megaxrom.jed file into the CPLD. Under
Linux I suggest that you use an alternative driver for Xilinx
iMPACT that works much better than the fragile windriver construct that
Xilinx uses. You can also get the source code
for the alternative driver for Xilinx iMPACT. Or you can also use other
JTAG interfaces which have a SVF or
XSVF player software, just use the
megaxrom.svf or megaxrom.xsvf file.
Version 1.4 is the first released version, anything earlier are
prototypes. Version 1.5 is nearly the same as version 1.4. The main change
is a simplification in the selection logic for flash ROM writes, the CS
signal is not necessary for movx write accesses. The other
differences are in the WebPACK version used to compile the design and some
minor documentation updates. The PCB layout is the same as for version 1.4.
I still keep version 1.4 available for download for people who don't want
to update their WebPACK.