Last changed: 2006-02-24

About the hardware

In this chapter I give a short overview about the video and sound hardware of the Videopac G7000 / Odyssey². For a much more complete overview see the "Odyssey² Technical Specs" at the home page from Daniel Boris.

P1: selection for `movx` access

The most important thing the 8048 port P1 controls is which chip is accessed by movx. It also supplies 2 address lines used for bank-switching and one signal to control the luminance of the video output.

P1.0 and P1.1	These signals are directly connected to the cart port pins 13 and 12. On most of the carts they are used as address lines A12 and A13. Some carts use them as enable signals for special bank switch methods.

P1.2	This signal is used to enable the keyboard decoder.
	This signal is used to enable the keyboard decoder.
P1.3	This is the select signal for VDC accesses. Setting it to 0 selects the VDC. Read accesses to the VDC need P1.6 to 0, too.

P1.4	This is the select signal for RAM accesses. Setting it to 0 selects RAM as external memory. For write accesses to RAM P1.6 has to be 0, too. This signal is also available at the cart port on pin 11.

P1.5	This signal is not used by the normal Videopac G7000 / Odyssey², but it is used as select signal for the EF9340/41 VPP chipset in the Videopac G7400. Setting it to 0 enables the VPP.

P1.6	This signal is used to be able to enable both RAM and VDC at the same time. Setting it to 1 turns off VDC read and RAM write accesses. Write accesses to the cart port get disabled, too. This allows you to read from RAM and write to VDC at the same time. The bios routines using the extram tables use this feature.

P1.7	This signal controls the luminance output of the VDC. See the chapter about tips and tricks for details.

VDC control, status and color

0A0h: `vdc_control`

This is the main control register of the VDC. It is a write-only register.

Bit 0	This bit enables an interrupt for every line on the screen.
	This bit enables an interrupt for every line on the screen.
Bit 1	This bit enables the position counters in the `vdc_scanline` and `vdc_scanrow` registers.

Bit 2	This bit enables an interrupt for sound.
	This bit enables an interrupt for sound.
Bit 3	If this bit is 1 the grid is displayed. If it is 0 the grid can be changed. If you change the grid registers while this is 1 the grid is not set to the correct values.

Bit 4	Unused.
	Unused.
Bit 5	If this bit is 1 sprites, chars and quads are displayed. If it is 0 they are turned off and can be changed. Changing sprites, chars and quads while this bit is 1 seems to have no effect.

Bit 6	This bit can be used to display a fixed dot grid.
	This bit can be used to display a fixed dot grid.
Bit 7	If this bit is set the vertical grid lines are extended to the right until the next grid line starts. So instead of lines you get boxes.

0A1h: `vdc_status`

This is the VDC status register. It is read-only.

Bit 0	This bit shows if the VDC is currently drawing a line or if it is in the HBLANK phase.

Bit 1	Shows if the scan counters `vdc_scanrow` and `vdc_scanline` are active.

Bit 2	Shows if the sound register is empty.
	Shows if the sound register is empty.
Bit 3	This bit show the start of the VBLANK.
	This bit show the start of the VBLANK.
Bit 4	Unused.
	Unused.
Bit 5	Unused.
	Unused.
Bit 6	Unused.
	Unused.
Bit 7	This bit is set when 2 or more chars/quads are overlapping each other.

0A2h: `vdc_collision`

This read/write register is used for collision detection. At VBLANK you need to set the bits for the objects you want collisions reported for. One frame later you can read what types of objects have collided. Here is an example: If you set only bit 0 and sprite 0 touches one of the chars one frame later the bits 0 and 7 are set.

Bit 0	This is the collision bit for sprite 0.
	This is the collision bit for sprite 0.
Bit 1	This is the collision bit for sprite 1.
	This is the collision bit for sprite 1.
Bit 2	This is the collision bit for sprite 2.
	This is the collision bit for sprite 2.
Bit 3	This is the collision bit for sprite 3.
	This is the collision bit for sprite 3.
Bit 4	This is the collision bit for the vertical grid lines.
	This is the collision bit for the vertical grid lines.
Bit 5	This is the collision bit for the horizontal grid lines.
	This is the collision bit for the horizontal grid lines.
Bit 6	Unused.
	Unused.
Bit 7	This is the collision bit for the chars/quads.
	This is the collision bit for the chars/quads.

0A3h: `vdc_color`

This register is used to set the background and grid color. The VDC generates a digital RGBI signal, one bit each for red, green, blue and intensity. The intensity bit for the background is always 0, so you can use normally only the 8 dark colors for the background. See the chapter about tips and tricks for a trick to use the 8 bright colors for the background.

Bit 0	This bit is the blue component for the grid color.
	This bit is the blue component for the grid color.
Bit 1	This bit is the green component for the grid color.
	This bit is the green component for the grid color.
Bit 2	This bit is the red component for the grid color.
	This bit is the red component for the grid color.
Bit 3	This bit is the blue component for the background color.
	This bit is the blue component for the background color.
Bit 4	This bit is the green component for the background color.
	This bit is the green component for the background color.
Bit 5	This bit is the red component for the background color.
	This bit is the red component for the background color.
Bit 6	This bit is the intensity component for the grid color.
	This bit is the intensity component for the grid color.
Bit 7	Unused.
	Unused.

0A4h: `vdc_scanline` and 0A5h: `vdc_scanrow`

If bit 1 of vdc_control is 1 the position of the currently generated pixel can be read from here. If vdc_control:1 is changed from 1 to 0 a snapshot of the current pixel position gets stored in vdc_scanline and vdc_scanrow. The X position in vdc_scanrow increments on every 0 to 1 transition of the VDC pixel clock input. The vdc_scanline register is incremented when the vdc_scanrow register changes from 0CEh to 0CFh. The vdc_scanrow register wraps around from 0E3h to 0.

0C0h-0E9h: VDC grid

The VDC can generate a grid with 10 vertical and 9 horizontal grid lines. There are separate register sets for the vertical and horizontal grid. Every column of grid parts has its own register. For every bit that is set the matching grid part is drawn. Bit 0 is the top most grid part. The registers 0C0h-0C8h (vdc_gridh0-vdc_gridh8) form the top 8 horizontal grid lines. The registers 0D0h-0D8h (vdc_gridi0-vdc_gridi8) control the last horitontal grid line, only bit 0 of this registers is used. The vertical grid is generated by the registers 0E0h-0E9h (vdc_gridv0-vdc_gridv9). The vertical grid lines can be displayed as blocks by setting a bit in vdc_control. It is also possible to display just dots on all positions where the horizonal and vertical grids cross. Before the grid can be changed it has to be turned off. Otherwise the changes are not correctly done.

VDC sprites

The VDC can generate 4 sprites of 8x8 pixels. The color for each sprite can be any of the 8 brighter colors, the intensity bit is always set. The sprite registers can only be changed when the foreground graphics is turned off.

080h-09fh: `vdc_spr`X`_shape`

These are the bitmap registers for the sprites, 8 for each sprite. When the sprites are displayed bit 0 is the leftmost pixel. So the look of the sprite is mirrored when written as binary number.

000h-00Fh: `vdc_spr`X`_ctrl`

These are the control registers for each sprite. Only 3 of them are used for each sprite, the fourth one is unused. There is no way to turn off the sprites individually, but when the position registers are set to 0F8h they are not displayed. This is the position used by the BIOS and I strongly recommend you use them too. Do not move the sprites just outside the visible area of your TV, they may still be visible on other TV sets and especially TV cards for PCs.

Sprite control 0		This register holds the Y position of the sprite.
		This register holds the Y position of the sprite.
Sprite control 1		This registers holds the 8 highest bits of the X position.
		This registers holds the 8 highest bits of the X position.
Sprite control 2		This register is used bitwise.
		This register is used bitwise.
	Bit 0	This is the lowest bit of the X position.
		This is the lowest bit of the X position.
	Bit 1	Setting this bit shifts the even rows of the sprite one pixel to the right.

	Bit 2	If this bit is 1 the size of the sprite doubles.
		If this bit is 1 the size of the sprite doubles.
	Bit 3	This bit is the red component for the sprite color.
		This bit is the red component for the sprite color.
	Bit 4	This bit is the green component for the sprite color.
		This bit is the green component for the sprite color.
	Bit 5	This bit is the blue component for the sprite color.
		This bit is the blue component for the sprite color.
	Bit 6	Unused.
		Unused.
	Bit 7	Unused.
		Unused.

VDC chars and quads

The VDC can generate up to 12 characters coming from a fixed character set of 64 different shapes. The bitmaps are 8x7 pixels big, the possible colors are the 8 bright colors, the intensity bit is always set. Officially the characters can't overlap each other. Ignoring this leads to a distorted display. A small overlap of less than 2 pixels in X direction seems ok. This means the X positions have to be at least 6 pixels apart. In the overlapping area the rightmost char gets displayed. The overlapping does not depend on the shape of the char, even spaces can't overlap. The charset pointer does not have to start at a character boundary, so it is possible to cut off the top part of a char, see tips and tricks for details.

Quads are very similar to chars. Every quad has 4 sub-quads. The relative positions of the sub-quads are fixed, they are 16 pixels apart, so there is a free space of 8 pixels between 2 sub-quads. The charset pointer and color registers are the same for chars and sub-quads, but there is only one set of position registers for the whole quad. All accesses on relative addresses 0, 4, 8 and 0Ch control the Y position, the addresses 1, 5, 9 and 0Dh control the X position. The overlapping rules apply to the quads, too. As the whole quad drawing is controlled by the last sub-quad it is possible to cut off the bottom of the first 3 sub-quads. See tips and tricks for details.

The char and quad registers can only be accessed when the foreground graphics is turned off. Any changes done when they are still active are ignored. Reading them does not return any sane values if the foreground graphics are enabled.

010h-07Fh: `vdc_char`X, `vdc_quad`X

Every char (and sub-quad) has a set of 4 control registers. Calculation of the charset pointer is a bit strange, to display the shape c in line Y you need to put c*8-Y/2 into the charset pointer. To turn off one char individually move it to position 0F8h/0F8h, just like a sprite. The X position resolution of the sprites is twice as fine as the X position resolution of the chars.

Char control 0		This register holds the Y position of the char.
		This register holds the Y position of the char.
Char control 1		This registers holds the X position of the char.
		This registers holds the X position of the char.
Char control 2		This register holds the lowest 8 bits of the charset pointer.

Char control 3		This register is used bitwise.
		This register is used bitwise.
	Bit 0	This is bit 8 of the charset pointer, the highest bit.
		This is bit 8 of the charset pointer, the highest bit.
	Bit 1	This bit is the red component for the char color.
		This bit is the red component for the char color.
	Bit 2	This bit is the green component for the char color.
		This bit is the green component for the char color.
	Bit 3	This bit is the blue component for the char color.
		This bit is the blue component for the char color.
	Bit 4	Unused.
		Unused.
	Bit 5	Unused.
		Unused.
	Bit 6	Unused.
		Unused.
	Bit 7	Unused.
		Unused.

Sound

The sound is generated by a 24 bit shift register. One bit at a time is shifted to the audio output. It is also possible to generate noise. The VDC supports 2 different sample rates. The higher frequency shifts out a bit every 4 lines, the lower every 16 lines. So the following sample shift rates are possible:

Machine	0AAh:5	Sample shift rate
Videopac	0	972 Hz
Videopac	1	3889 Hz
Odyssey²	0	981 Hz
Odyssey²	1	3925 Hz

0A7h-0A9h: `vdc_sound`X

This set of 3 registers form the 24 bit shift register.

0AAh: `vdc_soundctrl`

This is the sound control register, it is organized bitwise:

Bits 0-3	These 4 bits control the volume of the sound output.
	These 4 bits control the volume of the sound output.
Bit 4	This bit enables the noise generator.
	This bit enables the noise generator.
Bit 5	This bit controls the shift frequency.
	This bit controls the shift frequency.
Bit 6	If this bit is 1 the shift register is rotated, the last bit from the output is shift back into the other end.

Bit 7	If this bit is 0 the sound is turned off.
	If this bit is 0 the sound is turned off.

About the hardware

P1: selection for movx access

VDC control, status and color

0A0h: vdc_control

0A1h: vdc_status

0A2h: vdc_collision

0A3h: vdc_color

0A4h: vdc_scanline and 0A5h: vdc_scanrow